1. Field
The present invention generally relates to error-detection and error-correction mechanisms in computer memories. More specifically, the present invention relates to a computer system memory that supports guaranteed component-failure correction and double-error correction.
2. Related Art
Computer systems routinely employ error-detecting and error-correcting codes to detect and/or correct various data errors which are caused, for example, by noisy communication channels and unreliable storage media. Some error-detecting and error-correcting codes, such as single-error correction, double-error detection (SECDED) Hamming codes, can be used to correct single-bit errors and detect double-bit errors.
Other codes, which are based on Galois fields, can be used to correct a special class of multi-bit errors caused by a failure of an entire memory component. For example, see U.S. Pat. No. 7,188,296, entitled “ECC for Component Failures Using Galois Fields,” by inventor Robert E. Cypher, filed 30 Oct. 2003 (referred to herein as the “'296 patent”). The technique described in the '296 patent can “detect” double-bit errors which occur prior to a memory component failure. However, the technique cannot “correct” such double-bit errors. To provide higher levels of memory system reliability, it is desirable to be able to correct such double-bit errors.